Our SIMT (Single Instruction-flow Multiple Tasks) DSP is undoubtedly the most efficient architecture available today for use in baseband applications. The high performance, low cost/power and fast design-cycles makes it a perfect match for a broad range of systems implementations, for both single- and multi-mode products; wireless (LTE, HSPA, WLAN etc), broadcast (DVB and DAB) and wireline (cable modems).

Compared with commonly used VLIW DSP's, the SIMT DSP achieves higher hardware utilization and has a much smaller core size and a lower clock rate for the same application. In addition, the SIMT DSP is very easy and straightforward to use in development projects, co-simulated and implemented together with other functions to create complete systems-on-chip. Specific tasks/algorithms take fewer code lines to implement and the overall program code size is much smaller than for VLIW DSP's.

SIMT Architecture Overview

Key innovations

The SIMT Switch™ - does parallel direct streaming of data between any of the processor units. This enables much higher hardware utilization compared with traditional bus-based DSP’s. It also makes it very easy to fit new building blocks directly into the core of the architecture.

The SIMT Memory System™ - uses cacheless distributed memories which, in combination with the Switch, significantly reduces data memory size and memory accesses for cost and power savings. The addressing modes also support new types of algorithm implementations .

The SIMT Instruction Set™ - enables massive parallel processing control using low-complexity 24-bit instructions and a very programmer friendly code structure. It provides substantial overall core size, program line count, program code size & power consumption savings.

The SIMT Maker™ - does fast profiling and scaling of the entire core configuration, including customer specific function blocks, then automatically generates all RTL, simulator and toolkit code together with the core specific documentation.

SIMT Architecture advantages

• The SIMT DSP architecture is designed specifically for use in baseband applications and supports a wide range of standards very efficiently. Special care has been taken to optimize performance for the latest multi-carrier (OFDM) based standards used in 4G wireless and broadcast applications.
• The ability to realize complex system designs in firmware, still at the lowest cost and power, accelerates time to market for both initial development and later functionality upgrades of existing designs. Allowing re-use of a single die for multiple different products.
• The SIMT architecture enables new ways to implement system algorithms. For instance, sorting pilots in OFDM, typically a tedious DSP task, does not cost any extra clock cycles in the SIMT DSP, it is done by cleverly using the capabilities of our memory subsystem over the crossbar switch in combination with other symbol processing tasks.
• Clean hardware architecture; a single core for less complex applications like WLAN or DVB, one core for Rx and one for Tx for more complex standards like LTE and full scalability up to the cluster architectures required for pico/femto-cell base stations.
• Straightforward SIMT programming flow and Coresonic Developer Studio (CDS) saves time throughout the design cycle, from simulation and firmware coding to integration, tape-out and verification.
• The efficient SIMT instruction set and resulting small program code allows several different standards to reside in memory simultaneously, enabling rapid switching between modes. New modes can be added later in the product cycle, allowing easy updates of product lines.
• By using our Switch I/O specification it is very easy to fit new custom blocks directly into the architecture, fully supported by the simulator and other tools. It simplifies the integration process for customers wanting to re-use their existing hardware blocks.
• Flexible interfaces to common applications processors and easy implementation of MAC PHY control blocks facilitate porting of existing platforms, with no impact to existing MAC code base.
• Fast scaling of SIMT DSP architecture configurations with a profiler and graphical user interface, showing detailed resource utilization, enables fine tuning of performance for maximum hardware utilization (cost) and power optimization.
• It is easy to clock gate each individual unit attached to the crossbar switch, this allows implementation of advanced power saving schemes.
• The low cost and power of SIMT allows use of programmable SIMT DSP's in consumer applications where the use of DSP's were previously thought impossible. For example adding processor intense features to low-end wireless handsets or providing multiple diversity and multi-standard operation for low-cost mobile or fixed TV receivers.
• SIMT DSP's provide more than the required performance for the latest standards (LTE etc) at a fraction of the cost of alternative programmable solutions. This enables production worthy low-cost implementations already in the first generation of new chipsets.
• Our SIMT DSP innovations are based on a thorough understanding of communications systems and their algorithm implementations. You can do all systems development yourself or we can help with part or full implementations of the PHY layer according to your specification, including simulation, algorithm optimization and MAC interfacing. To prove our capabilities we are more than happy to take on customer specific evaluation demos prior to starting full scale projects.

For more information about our products and how we can give your products a competitive edge, please email us at sales@coresonic.com

Coresonic_IEEE_Sept09.pdf
Coresonic_IEEE_JSSC_Jan09.pdf

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